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cyd02s36v/36va flex36? 3.3 v (64 k 36) synchronous dual-port ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06076 rev. *l revised april 8, 2014 flex36? 3.3 v (64 k 36) synchronous dual-port ram features true dual-ported memory cells that enable simultaneous access of the same memory location synchronous pipelined operation pipelined output mode allows fast operation 0.18 micron complementary metal oxide semiconductor (cmos) for optimum speed and power high speed clock to data access 3.3 v low power ? active as low as 225 ma (typ.) ? standby as low as 55 ma (typ.) mailbox function for message passing global master reset separate byte enables on both ports commercial and industrial temperature ranges ieee 1149.1-compatible join t test action group (jtag) boundary scan 256 ball fine-pitch ball grid array (fbga) (1-mm pitch) counter wrap around control ? internal mask register co ntrols counter wrap-around ? counter-interrupt flags to indicate wrap-around ? memory block retransmit operation counter readback on address lines mask register readback on address lines dual chip enables on both ports for easy depth expansion seamless migration to next-generation dual-port family functional description the flex36? family includes 2-mbit pipelined, synchronous, true dual-port static rams that ar e high speed, low power 3.3 v cmos. two ports are provided, permitting independent, simultaneous access to any location in memory. a particular port can write to a certain location while another port is reading that location. the result of writing to the same location by more than one port at the same time is undefined. registers on control, address, and data lines allow for minimal setup and hold time. during a read oper ation, data is registered for decreased cycle time. each port contains a burst counter on the input address register. after externally loading the counter with the initial address, the counter increments the address internally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce0 or low on ce1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. one cycle with chip enables asserted is required to reactivate the outputs. additional features include: r eadback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (cntint ) flags, readback of mask register value on address lines, retransmit functionality, inte rrupt flags for message passing, jtag for boundary scan, and asynchronous master reset (mrst ). seamless migration to next-generation dual-port family cypress offers a migration path for all devices in this family to the next-generation devices in the dual-port family with a compatible footprint. please contact cypress sales for more details. product selection guide density 2-mbit (64 k 36) part number cyd02s36v/36va max. speed (mhz) 167 max. access time ? clock to data (ns) 4.4 typical operating current (ma) 225 package 256 fbga (17 mm x 17 mm)
cyd02s36v/36va document number: 38-06076 rev. *l page 2 of 29 logic block diagram ftsel l portstd[1:0] l dq [35:0] l be [3:0] l ce 0 l ce1 l oe l r/w l ftsel r portstd[1:0] r dq [35:0] r be [3:0] r ce 0 r ce1 r oe r r/w r a [15:0] l cnt/msk l ads l cnten l cntrst l ret l cntint l c l wrp l a [15:0] r cnt/msk r ads r cnten r cntrst r ret r cntint r c r wrp r config block config block io control io control dual ported array address & counter logic address & counter logic int l trst tms tdi tdo tck jtag mrst ready r lowspd r ready l lowspd l reset logic int r busy l busy r mailboxes arbitration logic
cyd02s36v/36va document number: 38-06076 rev. *l page 3 of 29 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 master reset ..................................................................... 6 mailbox interrupts ............................................................ 6 address counter and mask register operations .......... 6 counter reset operation ............................................ 7 counter load operation .............................................. 7 counter increment operation ...................................... 8 counter hold operation .............................................. 8 counter interrupt ......................................................... 8 counter readback operation ...................................... 8 retransmit ................................................................... 8 mask reset operation ................................................. 8 mask load operation .................................................. 8 mask readback operation .......................................... 8 counting by two ......................................................... 8 ieee 1149.1 serial boundary scan (jtag) [18] .............. 10 performing a tap re set ........................................... 10 performing a pause/restart ... ................................... 10 maximum ratings ........................................................... 12 operating range ............................................................. 12 electrical characteristics ............................................... 12 capacitance .................................................................... 12 switching characteristics .............................................. 13 jtag timing ................................................................... 14 jtag switching waveform ............................................ 15 switching waveforms .................................................... 15 ordering information ...................................................... 25 64 k 36 (2-mbit) 3.3 v synchronous cyd02s36v dual-por t sram ...... .............. 25 ordering code definitions ..... .................................... 25 package diagram ............................................................ 26 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 29 worldwide sales and design s upport ......... .............. 29 products .................................................................... 29 psoc? solutions ...................................................... 29 cypress developer community ................................. 29 technical support ................. .................................... 29
cyd02s36v/36va document number: 38-06076 rev. *l page 4 of 29 pin configurations figure 1. pin diagram - 256-ball fbga (top view) cyd02s36v/36va 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dq32l dq30l dq28l dq26l dq24l dq22l dq20l dq18l dq18r dq20r dq22r dq24r dq26r dq28r dq30r dq32r b dq33l dq31l dq29l dq27l dq25l dq23l dq21l dq19l dq19r dq21r dq23r dq25r dq27r dq29r dq31r dq33r c dq34l dq35l ret l [1,2] int l n c [1,4] n c [1,4] revl [1,3] trst [1,4] mrst nc [1,4] n c [1,4] n c [1,4] int r ret r [1,2] dq35r dq34r d a0l a1l wrp l [1,2] vrefl [1,3] ftsel l [1,2] lowsp d l [1,3] vss vttl vttl vss lowsp d r [1,3] ftsel r [ 1 ,2 ] vrefl [1,3] wrp r [1,2] a1r a0r e a2l a3l ce0 l ce1l vddiol vddiol vddiol vcore vcore vddio r vddio r vddio r ce1r ce0 ra3ra2r f a4l a5l cntint l be3 l vddiol vss vss vss vss vss vss vddio r be3 rcntint ra5r a4r g a6l a7l busy l [1,4] be2 l rev l [1,2] vss vss vss vss vss vss vddio r be2 r busy r [1,4] a7r a6r h a8l a9l cl vttl vcore vss vss vss vss vss vss vcore vttl cr a9r a8r j a10l a11l vss portst d1l [1,3] vcore vss vss vss vss vss vss vcore portstd 1r [1,3] vss a11r a10r k a12l a13l oe l be1 l vddiol vss vss vss vss vss vss vddio r be1 roe r a13r a12r l a14l a15l ads l be0 l vddiol vss vss vss vss vss vss vddio r be0 r ads ra15r a14r m nc [1,4] nc [1,4] r/w l revl [1,3] vddiol vddiol vddiol vcore vcore vddio r vddio r vddio r revr [1,3] r/w r nc [1,4] nc [1,4] n nc [1,4] nc [1,4] cnt/ msk l vrefl [1,3] portst d0l [1,3] ready l [1,4] rev l [1,2] vttl vttl rev r [1,2] ready r [1,4] portst d0r [1,3] vrefr [1,3] cnt/ msk r nc [1,4] nc [1,4] p dq16l dq17l cnten lcntrst l n c [1,4] n c [1,4] tck tms tdo tdi n c [1,4] n c [1,4] cntrst r cnten r dq17r dq16r r dq15l dq13l dq11l dq9l dq7l dq5l dq3l dq1l dq1r dq3r dq5r dq7r dq9r dq11r dq13r dq15r t dq14l dq12l dq10l dq8l dq6l dq4l dq2l dq0l dq0r dq2r dq4r dq6r dq8r dq10r dq12r dq14r notes 1. this ball represents a next generation dual-port feature. for more information about this feature, contact cypress sales. 2. connect this ball to vddio. for more information about this next generation dual-port feature contact cypress sales. 3. connect this ball to vss. for more information about this next generation dual-port feature, contact cypress sales. 4. leave this ball unconnected. for more informati on about this feature, contact cypress sales.
cyd02s36v/36va document number: 38-06076 rev. *l page 5 of 29 pin definitions left port right port description a 0l ?a 15l a 0r ?a 15r address inputs be 0l ?be 3l be 0r ?be 3r byte enable inputs . asserting these signals enables read and write operations to the corresponding bytes of the memory array. busy l [5,8] busy r [5,8] port busy output . when the collision is detected, a busy is asserted. c l c r input clock signal ce0 l ce0 r active low chip enable input ce1 l ce1 r active high chip enable input dq 0l ?dq 35l dq 0r ?dq 35r data bus input/output . oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrupt flag output . the mailbox permits communications between ports. the upper two memory locations can be used for message passing. int l is asserted low when the right port writes to the mailbox location of the left port, and vice versa. an interrupt to a port is deasserted high when it reads the contents of its mailbox. lowspd l [5,7] lowspd r [5,7] port low speed select input . portstd[1:0] l [5,7] portstd[1:0] r [5,7] port address/control/data io standard select inputs . r/w l r/w r read/write enable input . assert this pin low to write to , or high to read from the dual port memory array. ready l [5,8] ready r [5,8] port ready output . this signal is asserted when a port is ready for normal operation. cnt/msk l cnt/msk r port counter/mask select input . counter control input. ads l ads r port counter address load strobe input . counter control input. cnten l cnten r port counter enable input . counter control input. cntrst l cntrst r port counter reset input . counter control input. cntint l cntint r port counter interrupt output . this pin is asserted low when the unmasked portion of the counter is incremented to all ?1s?. wrp l [5,6] wrp r [5,6] port counter wrap input . the burst counter wrap control input. ret l [5,6] ret r [5,6] port counter retransmit input . counter control input. ftsel l [5,6] ftsel r [5,6] flow-through select . use this pin to select flow-t hrough mode. when is de-asserted, the device is in pipelined mode. vref l [5,7] vref r [5,7] port external high-speed io reference input . v ddiol v ddior port i/o power supply . rev l [5, 6, 7] rev r [5, 6, 7] reserved pins for future features. mrst master reset input . mrst is an asynchronous input signal and affects both ports. a maser reset operation is required at power up. trst [5,8] jtag reset input . tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck. tdi jtag test data input . data on the tdi input is shifted serially into selected registers. tck jtag test clock input . tdo jtag test data output . tdo transitions occur on the falling edge of tck. tdo is normally three-stated except when captured da ta is shifted out of the jtag tap. v ss ground inputs . notes 5. this ball represents a next generation dual-port feature. for more information about this feature, contact cypress sales. 6. connect this ball to vddio. for more information about this next generation dual-port feature contact cypress sales. 7. connect this ball to vss. for more information about this next generation dual-port feature, contact cypress sales. 8. leave this ball unconnected. for more informati on about this feature, contact cypress sales.
cyd02s36v/36va document number: 38-06076 rev. *l page 6 of 29 master reset the flex36 family devices undergo a complete reset by taking its mrst input low. the mrst input can switch asynchro- nously to the clocks. an mrst initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). mrst also forces the mailbox interrupt (int ) flags and the counter interrupt (cntint ) flags high. mrst must be performed on the flex36 family devices after power up. mailbox interrupts the upper two memory locations may be used for message passing and permit communications between ports. ta b l e 1 shows the interrupt operation for both ports of cyd02s36v/36va. the highest memory location, ffff is the mailbox for the right port and fffe is the mailbox for the left port. ta b l e 1 shows that to set the int r flag, a write operation by the left port to address ffff asserts int r low. at least one byte must be active for a write to generate an interrupt. a valid read of the ffff location by the right port resets int r high. at least one byte must be active in order for a read to reset the interrupt. when one port writes to the other port?s mailbox, the int of the port that the mailbox belongs to is asserted low. the int is reset when the owner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). each port can read the other po rt?s mailbox without resetting the interrupt. and each port can write to its own mailbox without setting the interrupt. if an application does not require message passing, int pins must be left open. address counter and mask register operations each port of these devices has a programmable burst address counter. the burst counter contai ns three registers: a counter register, a mask register, and a mirror register. the counter register contains the address used to access the ram array. it is changed only by the counter load, increment, counter reset, and by master reset (mrst ) operations. the mask register value affects the increment and counter reset operations by preventing the corresponding bits of the counter register from changing. it also affects the counter interrupt output (cntint ). the mask register is changed only by the mask load and mask reset operations, and by the mrst . the mask register defines the counting range of the counter register. it divides the counter register into two regions: zero or more ?0s? in the most signific ant bits define the masked region, one or more ?1s? in the least si gnificant bits define the unmasked region. bit 0 may also be ?0,? masking the least significant counter bit and causing the counter to increment by two instead of one. the mirror register is used to reload the counter register on increment operations (see ?retransmit,? below). it always contains the value last loaded in to the counter register, and is changed only by the counter load, and counter reset opera- tions, and by the mrst . table 2 on page 7 summarizes the operation of these registers and the required input control signals. the mrst control signal is asynchronous. all the other control signals in ta b l e 2 on page 7 (cnt/msk , cntrst , ads , cnten ) are synchronized to the port?s clk. all these count er and mask operations are independent of the port?s chip enable inputs (ce0 and ce1). notes 9. this family of dual-ports does not use v core , and these pins are internally nc. the next gener ation dual-port family, the flex36-e?, uses v core of 1.5 v or 1.8v. please contact local cypress fae for more information. 10. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data is out after the following clk edge and is three-stated after the next clk edge. 11. oe is ?don?t care? for mailbox operation. 12. at least one of be0 , be1 , be2 , or be3 must be low. 13. ?x? = ?don?t care,? ?h? = high, ?l? = low. v core [9] core power supply . v ttl lvttl power supply for jtag ios pin definitions (continued) left port right port description table 1. interrupt operation example [10, 11, 12, 13] function left port right port r/w l ce l a 0 l ?15 l int l r/w r ce r a 0r?15r int r set right int r flag l l ffff x x x x l reset right int r flag x x x x h l ffff h set left int l flag x x x l l l fffe x reset left int l flag h l fffe h x x x x
cyd02s36v/36va document number: 38-06076 rev. *l page 7 of 29 counter enable (cnten ) inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast, interleaved memory applications. a port?s burst counter is loaded when the port?s address strobe (ads ) and cnten signals are low. when the port?s cnten is asserted and the ads is deasserted, the address counter increments on each low to high transition of that port?s clock signal. this read?s or write?s one word from/into each successive addre ss location until cnten is deasserted. the counter can address the entire memory array, and loops back to the start. counter reset (cntrst ) is used to reset the unmasked portion of the burst counter to 0s. a counter-mask register is used to control the counter wrap. counter reset operation all unmasked bits of the counter and mirror registers are reset to ?0.? all masked bits remain unchanged. a mask reset followed by a counter reset resets the counter and mirror registers to 0000, as does master reset (mrst ). counter load operation the address counter and mirror registers are both loaded with the address value presented at the address lines. table 2. address counter and counter-mask register control operation (any port) [14, 15] clk mrst cnt/msk cntrst ads cnten operation description x l x x x x masterreset reset address counter to all 0s and mask register to all 1s. h h l x x counter reset reset counter unmasked portion to all 0s. h h h l l counter load load counter with external address value presented on address lines. h h h l h counter readback read out counter internal value on address lines. h h h h l counter increment internally increment address counter value. h h h h h counter hold constantly hold the address value for multiple clock cycles. h l l x x mask reset reset mask register to all 1s. h l h l l mask load load mask register with value presented on the address lines. h l h l h mask readback read out mask register value on address lines. h l h h x reserved operation undefined notes 14. ?x? = ?don?t care,? ?h? = high, ?l? = low. 15. counter operation and mask register operation is independent of chip enables.
cyd02s36v/36va document number: 38-06076 rev. *l page 8 of 29 counter increment operation once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addr essing the entire memory array. only the unmasked bits of the co unter register are incremented. the corresponding bit in the mask register must be a ?1? for a counter bit to change. the counte r register is incremented by 1 if the least significant bit is unma sked, and by 2 if it is masked. if all unmasked bits are ?1,? the next increment wraps the counter back to the initially loaded value. if an increment results in all the unmasked bits of the counter bei ng ?1s,? a counter interrupt flag (cntint ) is asserted. the next increment returns the counter register to its initial value, which was stored in the mirror register. the counter address can instead be forced to loop to 0000 by externally connecting cntint to cntrst . [16] an increment that results in one or more of the unmasked bits of the counter being ?0? de-asserts the counter interrupt flag. the example in figure 3 on page 10 shows the counter mask register loaded with a mask value of 003fh unmasking the first 6 bits with bit ?0? as the lsb and bit ?16? as the msb. the maximum value the mask register can be loaded with is ffffh. setting the mask register to this value allows the counter to access the entire memory space. the address counter is then loaded with an initial value of 8h. the base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. the counter address starts at address 8h. the counter increments its internal address value till it reaches the mask register value of 3fh. the counter wraps around the memory block to location 8h at the next count. cntint is issued when the counter reaches its maximum value. counter hold operation the value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. such operation is useful in applicati ons where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. counter interrupt the counter interrupt (cntint ) is asserted low when an increment operation results in the unmasked portion of the counter register being all ?1s.? it is deasserted high when an increment operation results in any other value. it is also de-asserted by counter reset, counter load, mask reset and mask load operations, and by mrst . counter readback operation the internal value of the counter register can be read out on the address lines. readback is pipelined; the address is valid t ca2 after the next rising edge of the port?s clock. if address readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) are three-stated. figure 2 on page 9 shows a block diagram of the operation. retransmit retransmit is a feature that allo ws the read of a block of memory more than once without the need to reload the initial address. this eliminates the need for external logic to store and route data. it also reduces the complexity of the system design and saves board space. an internal ?mirror register? is used to store the initially loaded address counter value. when the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this ?mirror register.? if the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the ?mirror register.? thus, the repeated access of the same data is allowed without the need for any external logic. mask reset operation the mask register is reset to al l ?1s,? which unmasks every bit of the counter. master reset (mrst ) also resets the mask register to all ?1s.? mask load operation the mask register is loaded wit h the address value presented at the address lines. not all values permit correct increment opera- tions. permitted values are of the form 2 n ? 1 or 2 n ? 2. from the most significant bit to the least significant bit, permitted values have zero or more ?0s,? one or mo re ?1s,? or one ?0.? thus ffff, 03fe, and 0001 are permitted values, but f0ff, 03fc, and 0000 are not. mask readback operation the internal value of the mask re gister can be read out on the address lines. readback is pipelined; the address is valid t cm2 after the next rising edge of the port?s clock. if mask readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) are three-stated. figure 2 on page 9 shows a block diagram of the operation. counting by two when the least significant bit of the mask register is ?0,? the counter increments by two. this may be used to connect the x36 devices as a 72-bit single port sram in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. this even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations. note 16. cntint and cntrst specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
cyd02s36v/36va document number: 38-06076 rev. *l page 9 of 29 from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to coun- ter bit 0 wrap figure 2. counter, mask, and mirror logic block diagram [1] 16 16 16 16 16 1 0 load/increment cnt/msk cnten ads cntrst clk decode logic bidirectional address lines mask register counter/ address register from address lines to readback and address decode 16 16 mrst
cyd02s36v/36va document number: 38-06076 rev. *l page 10 of 29 ieee 1149.1 serial boundary scan (jtag) [18] the flex36 family devices incorporate an ieee 1149.1 serial boundary scan test access port (tap). the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant taps. the tap operates using jedec-standard 3.3v io lo gic levels. it is composed of three input connections and one output connection required by the test logic defin ed by the standard. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the devices, and may be performed while the device is operating. an mrst must be performed on the devices after power up. performing a pause/restart when a shift-dr pause-dr shif t-dr is performed the scan chain outputs the next bit in the chain twice. for example, if the value expected from the chain is 1010101, the device outputs a 11010101. this extra bit causes some testers to report an erroneous failure for the devices in a scan test. therefore the tester must be configured to never enter the pause-dr state. 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 15 2 14 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 01 00 xs 1 x 0 x 0 x0 11 xs 1 x 1 x 1 x1 00 xs 1 x 0 x 0 x0 masked address unmasked address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register figure 3. programmable counter-mask register operation [17] table 3. identification register definitions instruction field value description revision number (31:28) 0h reserved for version number. cypress device id (27:12) c001h defines cypress part number for cyd02s36v/36va cypress jedec id (11:1) 034h allows unique ident ification of the dp family device vendor. id register presence (0) 1 indicates the presence of an id register. notes 17. the ?x? in this diagram represents the counter upper bits. 18. boundary scan is ieee 1149.1-compatible. see ?performing a pause/restart? for deviation from strict 1149.1 compliance.
cyd02s36v/36va document number: 38-06076 rev. *l page 11 of 29 table 4. scan register sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [19] table 5. instruction identification codes instruction code description extest 0000 captures the input/out put ring contents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places the register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces all device output drivers to a high-z state. clamp 0100 controls boundary to 1/0. places byr between tdi and tdo. sample/preload 1000 captures t he input/output ring contents. pl aces bsr between tdi and tdo. nbsrst 1100 resets the non-boundary scan logic. places byr between tdi and tdo. reserved all other codes other comb inations are reserved. do no t use other than the above. note 19. see details in the device bsdl files.
cyd02s36v/36va document number: 38-06076 rev. *l page 12 of 29 maximum ratings exceeding maximum ratings [20] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................. ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potentia l..............?0.5 v to +4.6 v dc voltage applied to outputs in high-z state ........................ ?0.5 v to v dd +0.5 v dc input voltage ............................ ?0.5 v to v dd + 0.5 v [21] output current into outputs (low)............................. 20 ma static discharge voltage.......................................... > 2000 v (jedec jesd22-a114-2000b) latch-up current..................................................... > 200 ma operating range range ambient temperature v ddio/vttl v core [22] commercial 0 c to +70 c 3.3 v165 mv 1.8 v100 mv notes 20. the voltage on any input or io pin cannot exceed the power pin during power up. 21. pulse width < 20 ns. 22. this family of dual-ports does not use v core , and these pins are internally nc. the next ge neration dual-port family, the flex36-e?, uses v core of 1.5v or 1.8v. please contact local cypress fae for more information 23. c out also references c io . electrical characteristics over the operating range parameter description -167 unit min typ max v oh output high voltage (v dd = min, i oh = ?4.0 ma) 2.4 ? ? v v ol output low voltage (v dd = min, i ol = +4.0 ma) ? ? 0.4 v v ih input high voltage 2.0 ? ? v v il input lowvoltage ? ? 0.8 v i oz output leakage current ?10 ? 10 ? a i ix1 input leakage current except tdi, tms, mrst ?10 ? 10 ? a i ix2 input leakage current tdi, tms, mrst ?1.0 ? 0.1 ma i cc operating current for (v dd = max.,i out = 0 ma), outputs disabled ? 225 300 ma i sb1 standby current (both ports ttl level) ce l and ce r ? v ih , f = f max ?90115ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max ? 160 210 ma i sb3 standby current (both ports cmos level) ce l and ce r ? v dd ? 0.2v, f = 0 ?5575ma i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max ? 160 210 ma i core [22] core operating current for (v dd = max, i out = 0 ma), outputs disabled ? 0 0 ma capacitance part number parameter [23] description test conditions max unit cyd02s36v/36va/ c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v 13 pf c out output capacitance 10 pf
cyd02s36v/36va document number: 38-06076 rev. *l page 13 of 29 figure 4. ac test load and waveforms switching characteristics over the operating range parameter description -167 unit cyd02s36v/cyd02s36va min max f max2 maximum operating frequency ? 167 mhz t cyc2 clock cycle time 6.0 ? ns t ch2 clock high time 2.7 ? ns t cl2 clock low time 2.7 ? ns t r [24] clock rise time ? 2.0 ns t f [24] clock fall time ? 2.0 ns t sa address setup time 2.3 ? ns t ha address hold time 0.6 ? ns t sb byte select setup time 2.3 ? ns t hb byte select hold time 0.6 ? ns t sc chip enable setup time 2.3 ? ns t hc chip enable hold time 0.6 ? ns t sw r/w setup time 2.3 ? ns t hw r/w hold time 0.6 ? ns t sd input data setup time 2.3 ? ns t hd input data hold time 0.6 ? ns t sad ads setup time 2.3 ? ns t had ads hold time 0.6 ? ns t scn cnten setup time 2.3 ? ns t hcn cnten hold time 0.6 ? ns t srst cntrst setup time 2.3 ? ns t hrst cntrst hold time 0.6 ? ns t scm cnt/msk setup time 2.3 ? ns t hcm cnt/msk hold time 0.6 ? ns t oe output enable to data valid ? 4.4 ns r1 = 590 ? r2 = 435 ? c = 5 pf (b) three-state delay (load 2) 90% 10% 3.0 v vss 90% 10% <2ns <2ns all input pulses 3.3 v v th = 1.5 v r = 50 ? z 0 = 50 ? (a) normal load (load 1) c = 10 pf output output note 24. except jtag signals (t r and t f < 10 ns [max.]).
cyd02s36v/36va document number: 38-06076 rev. *l page 14 of 29 t olz [25, 26] oe to low z 0 ? ns t ohz [25, 26] oe to high z 0 4.0 ns t cd2 clock to data valid ? 4.4 ns t ca2 clock to counter address valid ? 4.0 ns t cm2 clock to mask register readback valid ? 4.0 ns t dc data output hold after clock high 1.0 ? ns t ckhz [25, 26] clock high to output high z 0 4.0 ns t cklz [25, 26] clock high to output low z 1.0 4.0 ns t sint clock to int set time 0.5 6.7 ns t rint clock to int reset time 0.5 6.7 ns t scint clock to cntint set time 0.5 5.0 ns t rcint clock to cntint reset time 0.5 5.0 ns port to port delays t ccs clock to clock skew 5.2 ? ns master reset timing t rs master reset pulse width 5.0 ? cycles t rs master reset setup time 6.0 ? ns t rsr master reset recovery time 5.0 ? cycles t rsf master reset to outputs inactive ? 10.0 ns t rsint master reset to counter and mailbox interrupt flag reset time ? 10.0 ns switching characteristics over the operating range (continued) parameter description -167 unit cyd02s36v/cyd02s36va min max notes 25. this parameter is guaranteed by design, but it is not production tested. 26. test conditions used are load 2. jtag timing parameter description 167 unit min max f jtag maximum jtag tap controller frequency ? 10 mhz t tcyc tck clock cycle time 100 ? ns t th tck clock high time 40 ? ns t tl tck clock low time 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t tdih tdi hold after tck clock rise 10 ? ns t tdov tck clock low to tdo valid ? 30 ns t tdox tck clock low to tdo invalid 0 ? ns
cyd02s36v/36va document number: 38-06076 rev. *l page 15 of 29 jtag switching waveform test clock test mode select tck tms test data-in tdi te s t d a ta - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov switching waveforms figure 5. master reset mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t rsint
cyd02s36v/36va document number: 38-06076 rev. *l page 16 of 29 figure 6. read cycle [27, 28, 29, 30, 31] notes 27. ce is internal signal. ce = low if ce0 = low and ce1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk andcan be deasserted after that. data is out after the following clk edge and is three-stated after the next clk edge. 28. oe is asynchronously controlled; all other inputs (excluding mrst and jtag) are synchronous to the rising clock edge. 29. ads = cnten = low, and mrst = cntrst = cnt/msk = high. 30. the output is disabled (high-impedance state) by ce = v ih following the next rising edge of the clock. 31. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. switching waveforms (continued) t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency be0 ?be3 t sb t hb
cyd02s36v/36va document number: 38-06076 rev. *l page 17 of 29 figure 7. bank select read [32, 33] figure 8. read -to-write-to-read (oe = low) [34, 35, 36, 37, 38] notes 32. in this depth-expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress flex36 device fr om this data sheet. address (b1) = address (b2) . 33. ads = cnten = be0 ? be3 = oe = low; mrst = cntrst = cnt/msk = high. 34. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. 35. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 36. during ?no operation,? data in memory at the selected address may be corrupted and must be rewritten to ensure data integrit y. 37. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 38. ce 0 = be0 ? be3 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, since oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to thr ee-state the io for the write operation on the next rising edge o f clk. switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t dc t sd t hd write clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+2 a n+3 q n t ckhz no operation read
cyd02s36v/36va document number: 38-06076 rev. *l page 18 of 29 figure 9. read-to -write-to-read (oe controlled) [39, 40, 41, 42] figure 10. read with address counter advance [41] notes 39. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. 40. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 41. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 42. ce 0 = be0 ? be3 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, since oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to thr ee-state the io for the write operation on the next rising edge o f clk. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe q n+4 t cd2 t sa t ha t ch2 t cl2 t cyc2 clk address a n counter hold read with counter t sad t had t scn t hcn t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address ads cnten data out
cyd02s36v/36va document number: 38-06076 rev. *l page 19 of 29 figure 11. write with address counter advance [43] note 43. ce 0 = be0 ? be3 = low; ce 1 = mrst = cnt/msk = high. switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal data in address t sa t ha cnten ads
cyd02s36v/36va document number: 38-06076 rev. *l page 20 of 29 figure 12. counter reset [44, 45] notes 44. ce 0 = be0 ? be3 = low; ce 1 = mrst = cnt/msk = high. 45. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. 46. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [46] reset address 0 counter write read address 0 address 1 read read address a n address a m read
cyd02s36v/36va document number: 38-06076 rev. *l page 21 of 29 figure 13. readback state of address counter or mask register [47, 48, 49, 50] notes 47. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 48. address in output mode. host must not be driving address bus after t cklz in next clock cycle. 49. address in input mode. host can drive address bus after t ckhz . 50. an * is the internal value of the address counter (or the mask register depending on the cnt/msk level) being read out on the address lines. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n t sa t ha t sad t had t scn t hcn load address external t cd2 internal address a n+1 a n+2 a n t ckhz data out a n* q n+3 q n+1 q n+2 a n+3 a n+4 t cklz t ca2 or t cm2 readback internal counter address increment external a 0 ?a 16
cyd02s36v/36va document number: 38-06076 rev. *l page 22 of 29 figure 14. left_port (l_port) wr ite to right_port (r_port) read [51, 52, 53] notes 51. ce 0 = oe = ads = cnten = be0 ? be3 = low; ce 1 = cntrst = mrst = cnt/msk = high. 52. this timing is valid when one port is writing, and other port is reading the same location at the same time. if t ccs is violated, indeterminate data is read out. 53. if t ccs < minimum specified value, then r_port reads the most recent data (written by l_port) only (2 * t cyc2 + t cd2 ) after the rising edge of r_port's clock. if t ccs > minimum specified value, then r_port reads the most recent data (written by l_port) (t cyc2 + t cd2 ) after the rising edge of r_port's clock. switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk l r/w l a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 l_port address l_port data in clk r r/w r r_port address r_port data out
cyd02s36v/36va document number: 38-06076 rev. *l page 23 of 29 figure 15. counter interrupt and retransmit [54, 55, 56, 57, 58, 59] notes 54. x? = ?don?t care,? ?h? = high, ?l? = low. 55. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. 56. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 57. cntint is always driven. 58. cntint goes low when the unmasked portion of the address counter is incremented to the maximum value. 59. the mask register assumed to have the value of ffffh. switching waveforms (continued) t ch2 t cl2 t cyc2 clk fffd ffff internal address last_loaded last_loaded +1 t hcm counter fffe cntint t scint t rcint fffc cnten ads cnt/msk t scm
cyd02s36v/36va document number: 38-06076 rev. *l page 24 of 29 figure 16. mailbox interrupt timing [60, 61, 62, 63, 64] switching waveforms (continued) t ch2 t cl2 t cyc2 clk l t ch2 t cl2 t cyc2 clk r ffff t sa t ha a n+3 a n a n+1 a n+2 l_port address a m a m+4 a m+1 ffff a m+3 r_port address int r t sa t ha t sint t rint table 6. read/write and enable operation (any port) [65, 66, 67, 68] inputs outputs operation oe clk ce 0 ce 1 r/w dq 0 ? dq 35 x h x x high-z deselected x x l x high-z deselected xlhld in write llhhd out read h x l h x high-z outputs disabled notes 60. ce 0 = oe = ads = cnten = low; ce 1 = cntrst = mrst = cnt/msk = high. 61. address ?ffff? is the mailbox location for r_port of this device. 62. l_port is configured for write operation, and r_port is configured for read operation. 63. at least one byte enable (be0 ? be3 ) is required to be active during interrupt operations. 64. interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of th e read clock. 65. x? = ?don?t care,? ?h? = high, ?l? = low. 66. oe is an asynchronous input signal. 67. when ce changes state, deselection and read happen after one cycle of latency. 68. ce 0 = oe = low; ce 1 = r/w = high.
cyd02s36v/36va document number: 38-06076 rev. *l page 25 of 29 ordering code definitions ordering information 64 k 36 (2-mbit) 3.3 v synchronous cyd02s36v dual-port sram speed (mhz) ordering code package name package type operating range 167 cyd02s36va-167bbc bb256 256-ball bga commercial CYD02S36VA-167BBXC 256-ball bga pb-free temperature range: c = commercial x = pb-free; blank = non pb-free package type: bb = 256-ball bga speed grade: 167 mhz va = 3.3 v width: 36 = 36 s = sync density: 02 = 2 mb marketing code: d = dual-port sram company id: cy = cypress d cy 02 s - 167 c 36 va bb x
cyd02s36v/36va document number: 38-06076 rev. *l page 26 of 29 package diagram figure 17. 256-ball fbga (17 17 1.7 mm) package outline, 51-85108 51-85108 *i
cyd02s36v/36va document number: 38-06076 rev. *l page 27 of 29 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group sram static random access memory symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere ns nanosecond ? ohm pf picofarad v volt w watt
cyd02s36v/36va document number: 38-06076 rev. *l page 28 of 29 document history page document title: cyd02s36v/36va, flex36? 3.3 v (64 k 36) synchronous dual-port ram document number: 38-06076 rev. ecn no. orig. of change submission date description of change ** 232012 wwz see ecn new data sheet *a 244232 wwz see ecn changed pinout changed ftsel# to ftsel in the block diagram *b 313156 ydt see ecn c hanged pinout d10 fr om nc to vss to reflect test mode pin swap, c10 from rev[2,4] to vss to reflect sc removal. changed trscntint to trsint added trsint to the master reset timing diagram added cyd01s36v to data sheet added i sb5 and changed i ix2 *c 321033 ydt see ecn added cyd18s36v-133bbi to the ordering information section *d 327338 aeq see ec n change pinout c10 from vss to nc[2,5] change pinout g5 from vddio l to rev l [2,3] *e 365315 ydt see ecn added note for v core removed preliminary status *f 2193427 nxr / aesa see ecn changed t cd2 and t oe spec from 4ns to 4.4ns for -167. template update. *g 2623658 vkn / pyrs 12/17/08 added cyd02s36va-15axc part *h 2899734 vkn 03/26/2010 modified title on page 1 removed 1m, 4m, 9m, and 18m densities and their related information modified logic block diagram and pin configuration removed industrial operating grade removed 133 ns and 100ns speed bins removed ?bb256b? (23 x 23 x 1.7mm) 256-ball fbga package updated ordering information table updated ?bb256? (17 x 17 x 1.7mm) 256-ball fbga package diagram *i 3110296 admu 12/14/2010 updated ordering information . added ordering code definitions . *j 3202287 admu 03/22/2011 updated as per template updated notes added acronyms and units of measure table. *k 3843734 smch 12/17/2012 updated ordering information : added CYD02S36VA-167BBXC part. updated package diagram : spec 51-85108 - changed revision from *h to *i. *l 4336717 admu 04/08/2014 updated in new template.
document number: 38-06076 rev. *l revised april 08, 2014 page 29 of 29 flex36 and flex36-e are trademarks of cypress semiconductor corporation. all other trademarks or registered trademarks referenc ed herein are property of the respective corporations. all products and company names mentioned in this document may be the trademarks of their respective holders. cyd02s36v/36va ? cypress semiconductor corporation, 2004-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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